Memory using integrated circuits as unitary crosspoints



Dec. 8, 1970 1'. M. L. CAGNAC ET AL MEMORY USING INTEGRATED CIRCUITS ASUNITARY CROSSPOINTS Fi led Feb. 28, 1967 3 Sheets-Sheet 1 Inventorsmnese M. a. GAG/VAC ALA/N P. a GALL HA a .rawa

T.M. 1... CAGNAC ETAL 5 MEMORY USING INTEGRATED CIRCUITS AS UNITARYCROSSPOINTS Filed Feb. 28, 1967 Dec. 8, 1970 5 Sheets-Sheet 2 5 mm Nm rmlal ll'lll I I I I I I I I I l i l I i l I I I v 6 3m 5 Sm b w d H m 4Eu mmu -3 50 u n u 32 n b m bm m b bw n u m n m m n A a H M J" mu 8 0 $0Eu N42 q H H m A :b I 20 I flu :0 I

Dec. 8,1970 1', CAGNAC ETAL MEMORY USING INTEGRATED CIRCUITS AS UNITARYCROSSPOIN'I'S Filed Feb. 28, 1967 3 Sheets-Sheet 3 C 2 v Mi ha v mCGY nv 0 2% 1 m/ x H -MMM VIM/R United States Patent Office- 3,546,682Patented Dec. 8, 1970 Int. Cl. Gllb 11/43), 7/00; H03h 3/286 U.S. 01.340-173 2 Claims ABSTRACT OF THE DISCLOSURE A word-organized integratedcircuit elementary memory comprising a matrix of memory unit cells. Thecontrol signals of the memory cells are supplied by word logicalcircuits and by digit logical circuits. A word decoding circuit, inresponse to binary code signals, enables the selection of one of theword lines for a given opera tion.

The present invention concerns a non-destructive readout memory of smallcapacity which may be achieved by means of circuits known as integratedcircuits and which comprises, besides the memory elements themselves,the selection circuits for the read, write and clear operations.

In this memory, each unit cell is constituted by a flipfiop circuitrequiring a very low power for switching, so that the selection circuitsmay be achieved with active elements of the same type as those of thesaid flip-flop. The matrix memory and its selection circuits may begrouped on one same substrate of the integrated circuit. By Way ofexample, a word-organized memory according to the invention, for thestorage of sixteen words of four digits each, comprises only fourteenoutput conductors.

The active elements which have been mentioned may be either classicaltransistors such as planar-epitaxial transistors, or field-eifecttransistors. By way of a nonlimitative example one shall describe anintegrated circuit memory achieved by using classical transistors of theNPN type.

The object of the present invention is thus to realize a word-organizedmatrix memory which comprises its own selection circuits, said memorybeing so designed to minimize the number of output terminals and tofacilitate its achievement on a substrate of circuit known as integratedcircuit.

The present invention will be particularly described with reference tothe accompanying drawings in which:

FIG. 1 represents the detailed diagram of the memory unit cell;

FIG. 2 represents an elementary matrix memory;

FIG. 3 represents the circuit for complementing the operation signals;

FIG. 4 represents the Word decoding circuit;

FIG. 5 represents a word selection circuit;

FIG. 6 represents the digit selection circuit;

FIG. 7 represents a first alternative solution of the unit memory cell;

FIG. 8 represents a second alternative solution of the memory unit cell.

In the description of the circuits, the theshold voltage (base-emittervoltage drop Vbe for a normal transistor) and the collector-emittervoltage Vce of saturated or conducting transistors, will be taken intoaccount when required; the values of these voltages are respectively of0.6 volt and 0.2 volt for normal silicon transistors. The correspondingvoltages are generall higher in the case of field-effect transistors.

The unit memory cell shown on FIG. 1 may be of the type described in thepending application of A. J. L.

Chambet-Falquet-A. P. Le Gall-R. G. Yelloz, Serial No.

564,687 filed July 12, 1966, for a Non-Destructive Read- 5 out MemoryWith Short Access Time. In this figure, the

transistors 11 and 12 and the resistors 15 and 16 constitute a flip-flopof well-known configuration supplied by the positive voltage source V1.It will be assumed that this flip-flop is in the 1 state when thetransistor 12 is blocked, and that it is in the 0 state when thetransistor 11 is blocked. As a result, the point I is at a potential Vbeor Vce according to whether the flip-flop is in the 1 state or in the 0state. The transistors 13 and 14 are used for controlling the switchingof the flip-flop and the non-destructive readout of its state.

In order to study the operation of the memory cell, it will be assumedthat, at rest, all its output terminals are brought to the groundpotential except the output terminal CW which is brought to thepotential +V1. Under these conditions, the transistors 13 and 14 areblocked and the collectors of the transistors 11 and 12 are isolatedfrom the output terminals.

In order to write a digit 1, i.e. to set the flip-flop to the 1 state,the input LW is brought to the potential +V1 and the input CW to theground potential, so that the transistor 13 is saturated, the basecurrent being limited by the resistor 17. The transistor 12, the base ofwhich is thus brought to a voltage Vce, is blocked and the flipfiop setsto the 1 state. For reading the information written in the flip-flop,the inputs LR and CR are brought simultaneously to the potential +V1. Ifpoint I is at a potential Vbe or Vce substantially lower than Vl-Vbe,transistor 14 is saturated with a base current limited by the resistor18. The potential +V1 is applied to input CR through a resistor as shownin FIG. 6 (resistor 99) which will be described hereinafter so that acurrent flows through the transistor 14. The potential Vbe or Vce of thepoint I appears on the output CR except for the voltage drop Vce in thetransistor 14, an constitutes the readout signal of the memory cell.

Last, to reset the flip-flop to the 0 state, the input LZ is brought tothe potential +V1, so that the collector and the emitter of thetransistor 11 are at the same potential. If the flip-flop is in the 1state (the transistor 11 is saturated), the flip-flop resets to the 0state as the transistor 11 is blocked.

The memory cell just described is provided for constituting aword-organized matrix memory, and more precisely, an elementary memorywhich may be achieved in particular by using integrated circuits. Thiselementary memory comprises X lines 1, 2 x X and Y columns 1, 2 y Y forstoring X words each one comprising Y digits. The terminal references ofthis cell concern this arrangement and the first capital letter meansthat this terminal is connected either to a line or to a column,according to whether it is a L or a C.

The second reference letter W, R, Z concerns the opera-.

TABLE 1 Selection signals Rest Terminal voltage Writing Readout Clearing0 +V1 0 +V1 6 LZ 0 +V1 6 Operation signal W R Z a b c d Table Ihereabove represents, on the lines 1 to 5, the amplitudes of the signalsapplied to the terminals of a memory cell located at the intersection ofthe line x and the column 1 in the different operation phases juststudied. The columns a, 12, c, a are assigned to the voltages applied tothese terminals respectively when this cell is not selected (rest) orwhen it is selected for writing, read- 4 and eight identical wordselection circuits, such as the circuit Mx which delivers the signalcontrolling the selection of the word located on the line x. The circuitM0, which comprises the transistors 31 to 33 and the re sistors 35 to40, is identical to that described in FIG. 3

ing or clearing. 5 and delivers the signals fi, 2, 3

In order to facilitate the reading of the table, the volt- The circuitMx comprises the transistors 50 to S3 and ages which are not modifiedduring the consid red op rathe resistances 55 to 59. The first three ofthese trantions and which are the rest voltages shown in column a, i tera onn t d in u h a way a to form a threehave not been reported incolumns b, c, d. Line 6 shows 10 input; AND i it i hi h th point H isalways at the operation signals, W. R. Z, which control the executheground potential except when a signal of amplitude tiOIl Of a g, areading a Clearing in the i Cell- V1 is applied to all three inputs.Since this circuit is pro- The voltages shown on Table I have beenchosen suc vided for selecting a line under the control of the binary asa non-selected memory cell should not be disturbed, code 010, thesignals applied to these inputs are the sigduri g riti or reading, y theapplication of a single nals s1, and s3. The point H is thus at thepotential %1 t; t t 13 b t t d 1 h +V11 when the fline x is selected andthe corresponding HS, 6 1311518 01' Call e Saura 8 OIty W en igma be reerenced x t its p l I d CW h bf0ught, pi l l yt to The transistor 53constitutes an inverter circuit which POtentia S H an Zero- T eSaturatlon O t e deliver a signal 5 on its collector, this latter beingthus its 3.: iffififiifit 5:2 :52: assistants 252:: at e f t representsone o t e wor ogica c1rcu1 s, or durlng Yeadlng- The e e for theelearlng Whleh instance the circuit MLx reserved to the line x, WhichPehds y p the appheatloh Of a slgnal 011 the comprises the transistors61 to 66 and the resistors 68 li PI G t h t d to 76. Each one of thepairs of transistors 61-62, 63-64, rePresen h a SC ema 10 y 3 '9 6566,constitutes a two-input AND circuit similar to gahlzed Integratedclrcult elementary memory 13 Whlch the three-input AND circuit describedin relation with gfi fgi thgg sgieaizg tz ihfifg ifi 21 131 FIG. 4. Thefirst one of these circuits receives the sig- 1 1 nals W and 5, so thatit delivers a signal of amplitude C83, 08ft for those associated to thee1ghth l1ne. The +V1 on the Output LWx connected to the Y inputs LWcontrol signals of these memory cells are supplied by the of the Ymemory cells associated to the time x when Said 105ml F t MLZ MLS and bythe line is selected for a writing. In the opposite case, this dlgl?loglfial Plrcults B The Word output LWx is at the ground potential. Thesame goes Qodmg clrcuft MD enables the Selecnon of one of the for thesecond and third circuits which deliver signals llnes for a r ofamplitude +V1 respectively, on the output LRx and In order to simplifythe figure, the l eehductols on the output LZx which are multiplexed onthe Y inputs whlch are connected to t Input? LW, LZ of a LR and LZ ofthe Y cells of the line x. These three sigg have beenttgrsuped Into oneSmgle conductor beanng nals do have the required values for a correctoperation ti etrefereficetl 3. The satmg tgoes1 for thte tgg d g i ofthe memory cell such as they are shown in table I. 2; ax s; a g gg gi gg 40 FIG. 6 represents a digit logical circuit, for instance, thereference p g g the circuit BLy, as well as the write control circuitELy Each one of the word logical circuits supplies in paralfii l to gi iIt been Seen i i lel the Y cells associated to a line and this has beenshown t 15 clrcult 1c recelves a lgna Wy wh.en a dlglt must symbolicallyon FIG 1 by the multiplexing arrow placed be written 1n the column y, isplaced outside the elemenon the terminals LW, LZ, LR and bearing thereference 49 tary memory of and 1t Common to t the Y. In the same way,the multiplexing arrow placed on the columns of a memory Planeconstituted y a matrlx t i l CW, CR bears h reference X rangernent ofelementary memories. If this memory plane The ilalementary memory ofFIG. 2 comprises twelve 1s1 provlded forlthe storage of m.X words, thiscircuit suptermina s to which are a lied the su l volta e V1, pies inparalle the columns of the m elementar memthe ground potential, thesignals S1, 3, 53 wh ich conories located vertically. y y stitute-inbinary c0dethe number which enables the The circuit ELy comprises thetransistors PNP 90, 91 selection of one line, the complementary signalW, E Z and the resistors the Circuit of the operation signals definedpreviously and the colprises the transistors NPN 94, 95', 96 and theresistors umn selection signals during Writing. The terminals to 97, 98,99. In the circuit ELy, the resistors 100 and 93 which are applied thesesignals are referenced B1 to B4, are brought to a negative potential V2.

TABLE II Transistor B8 Et Bs EL Bs El E3 E1} Em Et Cl.

Writing +V1 Bl. +V1-Vce (92) St Bl. +V1 St Vce +Vl St Vce R0513 Ps 0.4V.Bl.

0 St -V2(92-100) Bl. +V1 Readout 0 Bl. Au Ps Au Bl.

and they are also used during reading for collecting the Table IIhereabove indicates the voltages which are readout signals. t present onsome of the electrodes of the transistors of 3 represents a elfellltWhleh Produces the COITI- these circuits, and their state in theditferent cases of plementary signals W, fi and Z of the operationsigoperation. The abbreviations of this table have the folnals, whichcomprises three inverter circuits constituted lowing meaning:

by the transistors 80 to 82 and the resistances 83 to 88.

It will be noted that this circuit is placed outside the elementarymemory of FIG. 2.

FIG. 4 represents the detailed diagram of the circuit Bs, Em, Cl. meanrespectively base, emitter and collector,

Et means state of a transistor,

BL, St, Ps means that the transistor considered is respec- MD of FIG. 2which comprises the group of inverters Mo tively blocked, saturated orconductive, this last state being, as the case may be that of thetransistor 95 in emitter-follower configuration.

It will be noted that the voltages shown in the columns 95 Bs and 94 Cl.are those appearing on the terminals CR3; and CWy connected respectivelyto all the terminals CR and CW of the memory cells associated to thecolumn y.

During the writing, the transistor 91 is saturated and the transistor95, the emitter of which is positive with respect to the base, isblocked. The transistors 94 and 96 are saturated thus bringing theconductors CWy and CRy to the ground potential (more precisely to thevoltage Vce). At the termination of the writing period, the transistor91 is blocked and the emitter of the transistor 95 is connected to thevoltage source V2 through the resistor 93.

During the rest periods, the potential of the terminal CRy (which is thebase of the transistor 95), is equal to +Vce, so that the emitter of thetransistor 95 is at the potential l-Vce-Vbe, or approximately 0.4 v.,this blocking the transistor 94. During the reading period, thisterminal CRy is brought to a potential Au equal either to Vce+Vce(approximately 0.4 v.) or to Vce+Vbe (approximately 0.8 v.), so that theemitter potential Au of the transistor 95 is either Vce+ Vce-Vbe(approximately 0.2 v.) or Vce+Vbe-Vbe (approximately +0.2 v.), these twovoltages constituting, as it has been explained hereabove, the outputsignals of the memory.

As stated hereinbefore, the elementary memory is designed to beconstructed in integrated circuit form and assembled in a multiplanematrix memory. The interconnections are carried out easily by weldingthe output terminals of the elementary memories on column and lineconductors engraved on double face printed circuits, or on multilayercircuits.

The number of outputs of an elementary memory for storing X words of Ydigits will now be determined by setting X :2, in order to minimize thenumber of terminals which are necessary for the line selection(terminals S1, S2, S3 in the example of FIG. 2). One has thus:

one ground terminal one supply terminal connected to the source +V1 aselection terminals three operation control terminals (signals ER, 2FIG. 2) Y column terminals (terminals B1 to B4, FIG. 2).

The total number of terminals of an elementary memory is thus: N=5+a+Y.

For instance, the various combinations of thirty-two unit cells give thefollowing results:

X=8 11:3 and Y=4 N=12 X=4 11:2 and Y=8 N=15 X=16 (1:4 and Y=2 N=11 X=2(1:1 and Y=8 N=14 The FIGS. 7 and 8 represent alternate solutions forthe unit memory cell, for which a certain number of components play thesame role as in the circuit of FIG. 1, and bear the same references.

In the circuit of FIG. 7, the emitter of the transistor 11 is groundedand the terminal LZ is connected, through the resistor 20, to the baseof a clearing transistor 19. It is seen that, when this transistor issaturated, the base of the transistor 11 is brought to the potential Vceso that this transistor is blocked if it were saturated, i.e. if theflip-flop was in the 1 state.

In the circuit of FIG. 8, a third control transistor 22 has been addedin the memory cell, and the terminal LW is connected to the base of thetransistors 13 and 22 through the resistors 17a and 17b. The clearingterminal is suppressed and terminals CW and CW0 are available, forcontrolling the switching of the flip-flop to the 1 or to the 0 state.The digit logical circuit is slightly, modified and an invertertransistor 24 with its resistors 25, 26 has been added. When theterminal By is brought to the ground potential, the transistors 94 and24 are respec- 6 tively blocked and saturated and the terminals CW andCWO are at the potentials and Vce, R1 and R2 representing the values ofresistors 25 and 98. When the terminal By is brought to the potential+V1, these terminals are brought to potentials Vce and +V1 (through theresistor 26). On the other hand, when the terminal LW is brought to theground potential (rest), none of the transistors 13 or 22 can besaturated. On the contrary, when this terminal LW is brought to thepotential +V1 (writing), the one among these transistors having itsemitter at the ground potential is saturated and the flip-flop sets tothe 1 state (if the terminal CW is at the ground potential) or to the 0state (if the terminal CWO is at the ground potential).

The description of the elementary memory according to the invention hasbeen made, by way of example, by using normal transistors. The samecirciuts may be used with field effect transistors achieved in the formof integrated circuits by using the corresponding voltage values. On theother hand, since the input impedance of these transistors is very high,all the resistors located in series in the control electrodes of thetransistors may be suppressed. These modifications are carried outwithout difficulty in the circuits of FIGS. 3, 4, 5.

What is claimed is:

1. A word-organized memory having X lines and Y columns comprising:

X -Y unit storage cells, each cell including a pair of cross-coupledtransistors and two associated transistors, each of said pair beingcoupled to an associated transistor, one of said associated transistorshaving a base terminal (LW) to which is applied a line write voltage andan emitter terminal (CW) to which is applied a column write voltage sothat said one associated transistors, in response to said voltagessaturates and sets said cross-coupled transistors into a staterepresentative of storing of an information, said other associatedtransistor having another base terminal (LR) to which is applied a lineread voltage and collector terminal (CR) to which is applied a columnread voltage, so that non-destructive sensing of the state of saidcross-coupled transistors is accomplished by applying said line readvoltage to said other base terminal (LR), and control terminal meanscoupled to said cross-coupled transistors for resetting saidcross-coupled transistor by applying a clearing voltage to said controlterminal means; and

selection means coupled to said X -Y storage cells including a source ofselection signals (S);

word decoding means having X-output terminal lines for translating saidsignals into a line selection signal on one out-of-X lines of saidoutput terminals;

an X word logical circuit coupled to each X-output terminal line, andlogical circuit having three output terminals connected respectively tosaid base terminal (LW), said other base terminal (LR), and said controlterminal (LZ) of said unit storage cells associated to the one out-of-Xlines;

a source of complementary write, read and clear signals (W, R Z) coupledto the input of said Word decoding means, and

a Y digit logical circuit having two output terminals connectedrespectively to said emitter terminal (CW) and collector terminal (CR)of said unit storage cell associated to said one out-of-X lines, andsaid Y logical circuit having an input termition signal on one out-of-xlines of said output terminals;

an X word logical circuit coupled to each X-output terminal line, and alogical circuit having three output terminals connected respectively tosaid base terminal (LW), said other base terminal (LR), and said controlterminal (LZ) of said unit storage cells associated to the one out-of-xlines; source of complementary write, read and clear 7 nal (B) on whichis applied, during a write operation, said column write voltage which iscoupled to said terminal (CW) and, during a read operation, on which ismeasured the state of a selected cross-coupled transistor. 2. Aword-organized memory having X lines and Y columns comprising:

X Y unit storage cells, each cell including a pair of cross-coupledtransistors having grounded emitters and two associated transistors,each of said pair being collector coupled to an associated 10 signals(W, R, 73) coupled to the input of said transistor, one of saidassociated transistors havword decoding means, and

ing a base terminal (LW) to which is applied a a Y digit logical circuithaving two output terminals line write voltage and an emitter terminal(CW) connected respectively to said emitter terminal to which is applieda column Write voltage so (CW) and collector terminal (CR) of said unitthat said one associated transistor, in response to storage cellassociated to said one out-of-X lines,

said voltages saturates and sets said cross-coupled and aid Y logicalcircuit having an input termitransistors into a state representative ofstoring nal (B) on which is applied, during a write of an information,said other associated tranoperation, said column write voltage which issistor having another base terminal (LR) to coupled to said terminal(CW) and, during a which is applied a line read voltage and collectorread operation, on which is measured the state terminal (CR) to which isapplied a column read of a selected cross-coupled transistor.

voltage, so that non-destructive sensing of the state of saidcross-coupled transistors is ac- References Cited complished by applyingsaid line read voltage UNITED STATES PATENTS to said other base terminal(LR), and a third associated transistor collector coupled to said3177373 4/1965 G m 340173X cross-coupled transistors and having a basecon- 3,177,374 4/ 1965 slmonlan et 307247X trol terminal (LZ) forresetting said cross- 3,364,362 1/1968 M6110 340-173X 3,417,265 12/1968Lee III 307-247 coupled transistor, by applying a clearing voltage tosaid control terminal; and

BERNARD KONICK, Primary Examiner selection means coupled to said X -Ystorage cells including a source of selection signals (S);

word decoding means having X-output terminal lines for translating saidsignals into a line selec- J. F. BREIMAYER, Assistant Examiner 35 US.Cl. X.R.

